Semiconductor device and manufacturing method thereof

ABSTRACT

A semiconductor device includes: a silicon substrate; and a field effect transistor including a gate insulating film over the silicon substrate, a gate electrode on the gate insulating film, and source and drain regions. The gate electrode includes, in part in contact with the gate insulating film, a crystallized Ni silicide region containing an impurity element of a conductivity type opposite to a conductivity type of a channel region in the field effect transistor.

TECHNICAL FIELD

The present invention relates to a semiconductor device having a fullsilicide gate electrode and a manufacturing method thereof, and moreparticularly to a technique for enhancing the performance andreliability of MOS type field effect transistors (MOSFET; Metal OxideSemiconductor Field Effect Transistor).

BACKGROUND ART

In the development of cutting-edge CMOS (complementary MOS) devices forwhich smaller and smaller transistors are required, the deterioration ofthe driving current due to the depletion of polycrystalline silicon(poly-Si) electrodes is posing a problem. In view of this problem, atechnique of preventing the deterioration of the driving current byapplying metal gate electrodes and thereby avoiding the depletion ofelectrodes is being studied.

The materials considered for use for the metal gate electrodes includepure metals, metal nitrides and silicides, but in any case it isrequired that the threshold voltages (Vth) of the n-type MOSFET(hereinafter “nMOS”) and the p-type MOSFET (hereinafter “pMOS”) can beset to appropriate levels.

Whereas it is required to set Vth to about ±0.1 eV for high performanceCMOS transistors, in order to meet this requirement it is necessary touse for the gate electrode a material of which the work function is notgreater than that of n-type poly-Si (4.0 eV) for nMOS or one of whichthe work function is not smaller than that of p-type poly-Si (5.2 eV)for pMOS.

As means of realizing these objectives, a method of controlling the Vthof transistors by separately using heterogeneous metals or alloys havingdifferent work functions for the gate electrodes of nMOS and pMOS (dualmetal gate technique) is proposed.

For instance, it is stated in Non-Patent Document 1 (Internationalelectron devices meeting technical digest 2002, p. 359) that the workfunctions of Ta and Ru formed on SiO₂ are 4.125 eV and 4.95 eV,respectively, and work function modulation by 0.8 eV is possible betweenthese two electrodes.

On the other hand, techniques regarding full silicide electrodes inwhich poly-Si is fully silicided with Ni, Hf, W or the like is nowattracting attention.

For instance, Patent Document 1 (U.S. Patent Application Laid-Open No.2005/0070062) discloses that, by using SiO₂ as the gate insulating filmand a silicide electrode obtained by full silicidation of poly-Si intowhich impurities including P and B have been implanted as the gateelectrode, (1) the formation process can be made more compatible withconventional CMOS processes and (2) the threshold voltage can becontrolled by adding impurities to poly-Si before silicidation overSiO₂.

This disclosure suggests that the full silicide electrode is a promisingmetal gate. In particular, the threshold control made possible by addingimpurities resulted in an effective work function of about 4.2 to 4.4 eVfor nMOS or about 4.7 to 4.9 eV for pMOS where impurities used inconventional semiconductor processes (B, Al, Ga, In and Ti for pMOS orN, P, As, Sb and Bi for nMOS) were applied. Such variations in thresholdoccur from the segregation of the added impurities on the silicideelectrode/SiO₂ gate insulating film interface by the so-called“snowplowing” effect at the time of silicidation. As the thresholdcontrol by the addition of impurities enables differentiated productionof pMOS and nMOS, it is considered a promising method for controllingthe threshold of transistors using SiO₂ as the gate insulating film.

Further, according to a technique described in Patent Document 2(Japanese Patent Application Laid-Open No. 2005-129551), where gateelectrodes have the Ni content of 30 to 60% and contain n-typeimpurities for nMOS and gate electrodes have the Ni content of 40 to 70%and contain p-type impurities for pMOS, effective work functions ofabout 4.1 eV and 5.1 eV have been obtained, respectively.

However, these techniques involve the following problems,

The dual metal gate technique for differentiated production ofheterogeneous metals or alloys having different work functions requiresa process for removing the metal layer deposited over either the pMOS ornMOS gate insulating film by etching, which deteriorates the quality ofthe gate insulating film during etching, thereby causing a drop in theperformance characteristics and reliability of the element.

When an NiSi electrode (nickel monosilicide electrode) obtained byimplanting an impurity such as P and B into poly-Si and fully silicidingthe poly-Si with Ni is used as the gate electrode on the SiO₂ gateinsulating film, the effective work function achieved for nMOS is about4.2 to 4.4 eV or the effective work function achieved for pMOS is about4.7 to 4.9 eV, as described above, but realization of a high performancetransistor requires achievement of a lower threshold by controlling theeffective work function.

According to Patent Document 2, where gate electrodes have the Nicontent of 30 to 60% and contain n-type impurities for nMOS and gateelectrodes have the Ni content of 40 to 60% and contain p-typeimpurities for pMOS, effective work functions of about 4.1 eV and 5.1 eVare obtained, respectively. However, no Ni silicide electrode havingeffective work functions permitting achievement of a threshold requiredfor realizing high performance nMOS and pMOS in this composition region(4.0 eV for nMOS and 5.2 eV for pMOS) has been discovered as yet.

As the tightness of adhesion between the gate electrode and SiO₂ gateinsulating film is very poor when the Ni content of the gate electrodeis 40% or above, the gate electrode/insulating film interface is apt tocome off, often causing a deterioration in element performance. Also,when the Ni content of the gate electrode is 40% or above, compressivestress attributable to the electrode is known to work on the gateinsulating film and result in a drop in the reliability of the gateinsulating film (International electron devices meeting technical digest2005, p. 709). By reason of these points, it is preferable for the Nicontent of the Ni silicide electrode to be less than 40%, but no Nisilicide electrode capable of realizing a threshold needed for highperformance pMOS in this content region has been discovered as yet.

In fabricating a CMOS device, it is preferable for both nMOS and pMOSsilicide electrodes to be formed in one round of silicidation with aview to cost reduction through simplification of the process. To achievethis purpose, it is necessary for the nMOS and pMOS Ni full silicidegate electrodes to have the same composition, but no Ni silicideelectrode having effective work functions to permit realization ofthresholds needed for a high performance CMOS device (4.0 eV for nMOSand 5.2 eV for pMOS), while the silicides that constitute the nMOS andpMOS gate electrodes have the same composition, has been discovered asyet.

It is also required, along with the miniaturization of elements, torestrain unevenness of the thresholds of transistors.

DISCLOSURE OF THE INVENTION

An object of the present invention is to provide a semiconductor deviceenhanced in the performance and reliability of elements and amanufacturing method thereof.

According to the invention, the following semiconductor devices andmanufacturing methods thereof are provided.

(1) A semiconductor device including:

a silicon substrate; and

a field effect transistor including a gate insulating film over thesilicon substrate, a gate electrode on the gate insulating film, andsource and drain regions, wherein

the gate electrode includes, at least in part in contact with the gateinsulating film, a crystallized Ni silicide region containing animpurity element of a conductivity type opposite to a conductivity typeof a channel region in the field effect transistor.

(2) The semiconductor device according to item 1, wherein the silicidemaking up the crystallized Ni silicide region has a compositionrepresented by Ni_(x)Si_(1-x)(0.2≦x<0.4).

(3) The semiconductor device according to item 1 or 2, wherein thesilicide making up the crystallized Ni silicide region includes an NiSi₂phase.

(4) The semiconductor device according to any one of items 1 to 3,wherein the silicon substrate includes, at least in part in contact withthe gate insulating film, a region containing fluorine atoms in the caseof a P-channel transistor and a region containing nitrogen atoms in thecase of an N-channel transistor.

(5) A semiconductor device including:

a silicon substrate;

a P-channel field effect transistor including a first gate insulatingfilm over the silicon substrate, a first gate electrode on the firstgate insulating film, and first source and drain regions; and

an N-channel field effect transistor including a second gate insulatingfilm over the silicon substrate, a second gate electrode on the secondgate insulating film, and second source and drain regions, wherein

the first gate electrode includes, at least in part in contact with thefirst gate insulating film, a crystallized Ni silicide region containingp-type impurities, and

the second gate electrode includes, at least in part in contact with thesecond gate insulating film, a crystallized Ni silicide regioncontaining n-type impurities.

(6) The semiconductor device according to item 5, wherein the silicidesmaking up the crystallized Ni silicide regions of the first and secondgate electrodes have a composition represented byNi_(x)Si_(1-x)(0.2≦x<0.4).

(7) The semiconductor device according to item 5, wherein the silicidesmaking up the crystallized Ni silicide regions of the first and secondgate electrodes includes NiSi₂ phases.

(8) The semiconductor device according to any one of items 5 to 7,wherein the first and second gate electrodes include, in respectiveparts in contact with the first and second gate insulating films,regions containing an impurity element of a higher concentration thanabove the regions,

(9) The semiconductor device according to any one of items 5 to 8,wherein the first and second gate electrodes include, in respectiveparts in contact with the first and second gate insulating films,regions having impurity concentration of 1×10²⁰ cm⁻³ or above.

(10) The semiconductor device according to any one of items 5 to 9,wherein the first and second gate insulating films are silicon oxidefilms or silicon oxynitride films.

(11) The semiconductor device according to any one of item 5 to 9,wherein the first and second gate insulating films include silicon oxidefilms, silicon oxynitride films or silicon nitride films respectively incontact with the first and second gate electrodes.

(12) The semiconductor device according to any one of items 5 to 11,wherein the silicon substrate includes, at least in part in contact withthe first gate insulating film, a region containing fluorine atoms.

(13) The semiconductor device according to any one of items 5 to 12,wherein the silicon substrate includes, at least in part in contact withthe second gate insulating film, a region containing nitrogen atoms.

(14) A method of manufacturing the semiconductor device as described initem 5, including:

providing a silicon substrate including an n-type active region and ap-type active region;

forming a insulating film for first and second gate insulating filmsover the silicon substrate;

forming a silicon film for gate over the insulating film;

adding p-type impurities to the silicon film for gate in a region wherea P-channel field effect transistor is to be formed;

adding n-type impurities to the silicon film for gate in a region wherea N-channel field effect transistor is to be formed;

forming a gate pattern by processing the silicon film for gate;

forming first source and drain regions in the region where the P-channelfield effect transistor is to be formed;

forming second source and drain regions in the region where theN-channel field effect transistor is to be formed;

forming an interlayer insulating film so as to cover the gate pattern,

removing upper part of the interlayer insulating film so as to exposethe gate pattern;

forming a nickel film over the exposed gate pattern;

conducting heat treatment to silicide the gate pattern, thereby formingfirst and second gate electrodes; and

selectively removing superfluous nickel of unsilicided part of thenickel film.

(15) The semiconductor device manufacturing method according to item 14,wherein the p-type impurities and the n-type impurities are added by ionimplantation.

(16) The semiconductor device according to item 14 or 15, furtherincluding: adding fluorine to the silicon substrate in the region wherethe P-channel field effect transistor is to be formed before forming theinsulating film for the first and second gate insulating films.

(17) The semiconductor device according to any one of item 14 to 16,further including: adding nitrogen to the silicon substrate in theregion where the N-channel field effect transistor is to be formedbefore forming the insulating film for the first and second gateinsulating films.

According to the invention, a transistor having high performance andreliability and a simple method of manufacturing the same can beprovided.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic sectional view illustrating a semiconductor devicein accordance with an exemplary embodiment of the invention;

FIG. 2 is a diagram showing the relationship between the composition ofcrystallized Ni silicide and the film thickness ratio betweenpolycrystalline silicon before silicidation and Ni (Ni film thickness/Sifilm thickness);

FIG. 3 is a diagram showing the relationship among the effective workfunction of crystallized Ni silicide, Ni content and the effect ofaddition of impurities;

FIG. 4 is a diagram illustrating the range of thresholds of transistorsthat can be realized with work functions of silicide electrodesfabricated according to an exemplary embodiment of the invention;

FIG. 5 are sectional views of steps of a semiconductor devicemanufacturing method in accordance with an exemplary embodiment of theinvention;

FIG. 6 are sectional views of steps of the semiconductor devicemanufacturing method in accordance with the exemplary embodiment of theinvention;

FIG. 7 are diagrams showing the results of measurement of the draincurrent-gate voltage characteristics of a MOSFET fabricated according tothe invention (FIG. 7( a) shows the measurement results for nMOS andFIG. 7( b), those for pMOS);

FIG. 8 is a diagram showing the relationship between the composition ofNi silicide according to the related art (comparative example) and thefilm thickness ratio between polycrystalline silicon and Ni beforesilicidation;

FIG. 9 is a diagram showing the relationship between the effective workfunction of Ni silicide according to the related art (comparativeexample) and the Ni content;

FIG. 10 is a diagram showing the unevenness of the thresholds oftransistors fabricated according to the invention and the related art(comparative example);

FIG. 11 are sectional views of steps of a semiconductor devicemanufacturing method in accordance with a second exemplary embodiment ofthe invention;

FIG. 12 are sectional views of steps of the semiconductor devicemanufacturing method in accordance with the second exemplary embodimentof the invention;

FIG. 13 are sectional views of steps of the semiconductor devicemanufacturing method in accordance with the second exemplary embodimentof the invention;

FIG. 14 is a schematic sectional view illustrating a semiconductordevice in accordance with another exemplary embodiment of the invention;

FIG. 15 are sectional views of steps of a semiconductor devicemanufacturing method in accordance with a third exemplary embodiment ofthe invention;

FIG. 16 is a schematic sectional view illustrating a semiconductordevice in accordance with the third exemplary embodiment of theinvention;

FIG. 17 is a diagram illustrating the range of thresholds of transistorsthat are fabricated according to the third exemplary embodiment of theinvention (fluorine added); and

FIG. 18 is a diagram illustrating the range of thresholds of transistorsthat are fabricated according to the third exemplary embodiment of theinvention (nitrogen added).

BEST MODE FOR CARRYING OUT THE INVENTION

The present invention will be described in detail below with referenceto exemplary embodiments thereof.

The invention is based on the following facts which were newlydiscovered.

When a gate electrode made up of highly crystalline Ni silicide to whichimpurity elements have been added is formed over a gate insulating film,the variation of the effective work function due to the addition of theimpurity elements (the difference between the case in which the impurityelements have been added and the undoped case) increases along with adecrease in the Ni content of the silicide, and an effective workfunction more suitable for threshold control than what is based on therelated art can be realized. In particular, where a crystallized Nisilicide whose Ni content is less than 40% and to which impurityelements have been added is used for a gate electrode, a pMOS and annMOS lower in threshold than what is based on the related art can berealized.

The findings above were derived from the following preliminaryexperiment using MOS capacitances.

First, an SiO₂ gate insulating film (thickness: 3 nm) was formed over asilicon substrate, and a polycrystalline silicon (poly-Si) film of 80 nmin thickness was formed over that film.

Next, impurity elements were ion-implanted into the poly-Si film. Theadded impurity elements were of a conductivity type opposite to that ofthe channel region of a transistor (namely the conductivity typeopposite to the conductivity type of the silicon substrate active regionimmediately underneath the gate insulating film where the channel isformed). For instance, in order to realize an nMOS, N, P, As, Sb, Bi andso forth which are n-type impurities with respect to Si, and to realizea pMOS, B, Al, In, Ga, TI and so forth which are p-type impurities withrespect to Si can be ion-implanted.

After that, an Ni film (thickness: T_(Si)) was deposited over thepoly-Si film (thickness: T_(Ni)), followed by heat treatment to fullysilicide the poly-Si film.

Table 1 shows the thickness ratio between the poly-Si film (Si film)before the silicidation and the Ni film on one hand and the type of thecrystalline phase of the nickel silicide formed by the silicidation onthe other.

As shown in Table 1, the crystalline phase of the nickel silicide isdetermined stepwise relative to the thickness of the Ni film depositedover the poly-Si film, namely the quantity of Ni supplied to poly-Si.For instance, when it is desired to make the crystalline phase of the Nisilicide near the gate electrode/insulating film interface, whichaffects the effective work function, mainly an NiSi phase, the ratio(T_(Ni)/T_(Si)) between the thickness (T_(Si)) of the poly-Si film andthe thickness (T_(Ni)) of the Ni film can be set in the range between0.55 and 0.95 or, when it is desired to make it mainly an Ni₃Si phase,T_(Ni)/T_(Si) can be set to 1.6 or above. When it is desired to make thecrystalline phase of Ni silicide near the gate electrode/insulating filminterface a silicide whose main component is an NiSi₂ phase, it isnecessary to set T_(Ni)/T_(Si) in the range between 0.28 and 0.54 andthe silicidation temperature to not less than 600° C., or morepreferably not less than 650° C. As the composition ratio (Ni/(Ni+Si))which determines the work function of the Ni silicide is determined in avirtually self-matching manner by the formation of the crystalline phasesuch as NiSi₂, NiSi or Ni₃Si, the margins allowed for the processconditions including the Ni film thickness and the silicidationtemperature for obtaining the same crystalline phase (namely forobtaining the same work function) are broad, making it possible torestrain fluctuations attributable to the manufacturing process.

TABLE 1 Ratio of Ni film thickness/Si film thickness 0.28-0.54 0.55-0.951.6 or above Annealing 650° C. NiSi₂ temperature (+NiSi) 600° C. NiSi500° C. NiSi NiSi Ni₃Si (+NiSi) 450° C. NiSi Ni₃Si (+NiSi) 400° C. NiSiNi₃Si (+NiSi)

During this full silicidation, impurity elements were segregated nearthe silicide electrode/insulating film interface by the “snowplowing”effect. At that time, when the concentration of the segregated impurityelements fell below 1×10²⁰ cm⁻³ near that interface, the effective workfunction hardly varied. Therefore, in order to vary the effective workfunction, it is preferable to have, in the gate electrode part near thegate electrode/gate insulating film interface, a segregated impuritiesregion containing impurities of a higher concentration than aboveregion, and it is preferable for the impurities concentration in thesegregated impurities region to be not below 1×10²⁰ cm⁻³. On the otherhand, from the viewpoint of reliability of elements, it is preferablefor the concentration of the impurities of this segregated impuritiesregion to be not higher than 1×10²³ cm⁻³, and even more preferable to benot higher than 5×10²² cm⁻³. Thus, it is preferable for the gateelectrode for use in the invention to contain impurity elements in theconcentration range stated above in the part in contact with the gateinsulating film. It is also preferable for the impurities region(segregated impurities region) in this concentration range in the gateelectrode to be present for 5 nm or more in the thickness direction (thedirection perpendicular to the substrate plane) from the gateelectrode/insulating film interface.

The crystalline phase of the Ni silicide of the MOS capacitancefabricated as described above was identified by XRD. As shown in Table1, where T_(Ni)/T_(Si)=0.28 to 0.54, the Ni silicide that is formedsubstantially is made up of NiSi₂. However, in XRD, NiSi₂ is weak inpeak intensity, and a peak of NiSi is witnessed. According to ananalysis of the silicide electrode composition in the depthwisedirection by XPS, a slightly higher Ni content than that in NiSi₂ isfound on the electrode surface side, and therefore NiSi is presentmainly in that part. Where T_(Ni)/T_(Si)=0.55 to 0.95, the Ni silicidethat is formed is substantially made up of NiSi. Where T_(Ni)/T_(Si) is1.6 or above, the Ni silicide that is formed is substantially made up ofNi₃Si.

FIG. 2 shows the relationship between the Ni content in the electrodenear the electrode/insulating film interface of the MOS capacitancefabricated as described above and the ratio (T_(Ni)/T_(Si)) of the Nifilm thickness before silicidation/poly-Si film thickness (Si filmthickness). The Ni content in the electrode was figured out from the XPSmeasurement, The error bars of electrode composition representfluctuations in the multi-point XPS measurement.

It is seen from this diagram that the Ni content in the electrode nearthe interface is determined stepwise according to the T_(Ni)/T_(Si)ratio. For instance, at T_(Ni)/T_(Si)=0.28 to 0.54, 0.55 to 0.95 and 1.6or above, the Ni content in the electrode near the interface wasrespectively 33.3±7%, 50±5% and 75±5%. These compositions havesubstantially corresponded to the Ni content of NiSi₂ (33.3%), the Nicontent of NiSi (50%), and the Ni content of Ni₃Si (75%), respectively.This is probably due to the self-matching determination of the Nicontent in the electrode near the interface by the crystalline phase asshown in Table 1.

FIG. 3 shows, with respect to the MOS capacitance fabricated asdescribed above, the relationships between the effective work functionof crystallized Ni silicide and the silicide electrode composition nearthe interface in the case where no impurity elements have been added(undoped), in the case where As has been added, and in the case where Bhas been added (the doses of As and B added into poly-Si are both 5×10²⁰cm⁻³). The error bars of electrode composition represent fluctuations inthe multi-point XPS measurement. The figure shows the main crystallinephase in that composition.

As is seen from this figure, when no impurity elements have been added,the effective work function of the crystallized Ni silicide is hardlydependent on the composition. Therefore, even if the Ni contentfluctuates by ±5% or so, fluctuations of the threshold can berestrained.

To look at the cases in which any impurity has been added, the variationof the effective work function due to the impurity addition (thedifference between the case in which any impurity has been added and theundoped case) increases with a decrease in the Ni content (an increasein the Si content). In particular, in the region in which the Ni contentis from 26 atom % to 40 atom % where the main crystalline phase isNiSi₂, the effective work function is 4.0 eV under doping with As or 5.2eV under doping with B, indicating that an effective work functionrequired for high performance CMOSFET device (4.0 eV or less for nMOS,5.2 eV or above for pMOS) can be realized.

The tendency of the variation of the effective work function due to theimpurity addition to increase with a decrease in the Ni content in theNi silicide (an increase in the Si content) was confirmed with everyimpurity having the effect to modulate the work function. In particular,the effective work function in crystallized NiSi₂ was 4.0 eV or lesswith n-type impurities (N, P, As, Sb, Bi and so forth) and 5.2 eV ormore with p-type impurities (B, Al, In, Ga, TI and so forth), whichdemonstrates that the effective work function requirement for highperformance CMOS devices (4.0 eV or less for nMOS, 5.2 eV or above forpMOS) can be achieved.

This dependence of the variation of the effective work function due toimpurity addition on the Ni content in the electrode is entirelydifferent from the tendency disclosed in Japanese Patent ApplicationLaid-Open No. 2005-129551 (Patent Document 2). In particular, where anyp-type impurity is added, the resultant trend of the dependence of theeffective work function on the Ni content in the electrode is reversebetween this exemplary embodiment and the case of Patent Document 2.

This is attributable to the following reason. In the case of PatentDocument 2, the variation of the effective work function due to impurityaddition (the difference between the case in which any impurity has beenadded and the undoped case) is dependent solely on the type and quantityof the impurity, but hardly on the composition of the Ni silicideelectrode. Further, the effective work function of an undoped Nisilicide electrode rises (from 4.43 eV to 5.1 eV) with an increase inthe Ni content (from 30 atom % to 100 atom %). In the case of thisexemplary embodiment, unlike that, the effective work function of theundoped crystallized Ni silicide is hardly dependent on the Ni content,and the variation of the effective work function increases with adecrease in the Ni content (an increase in the Si content) as shown inFIG. 3. In this way, the present invention and the technique accordingto Patent Document 2 are greatly different in the dependence of thevariation of the effective work function due to impurity addition on thecomposition of the electrode. This difference is probably attributableto a difference in crystallinity resulting from a difference information method as will be described afterwards with reference to thecomparative example.

As shown in FIG. 3, the effective work function of the doped Nisilicide, as it is affected by the Ni content, it is preferable to forma silicide in which the Ni content is determined in a self-matchingmanner, Namely, it is preferable to form a silicide whose maincrystalline phase is a thermodynamically stable crystalline phase,especially to form a silicide whose main crystalline phase is a NiSi₂crystalline phase. As stated above, since the formation of the NiSi₂crystalline phase causes the Ni content to be determined in aself-matching manner, the margins allowed for the process conditions arebroad, making it possible to restrain fluctuations of the Ni contentattributable to the manufacturing process. Thus, according to thepresent invention in which doped crystallized NiSi₂ may be applied tothe gate electrode, as the electrode composition is determined at thetime of full silicidation in a self-matching manner, it is made possibleto form a transistor whose threshold fluctuations are restrained.Further, as a silicide whose Ni content is less than 40 atom % can beformed, the adhesion between the silicide electrode and the gateinsulating film is tightened, and a compressive stress on the gateinsulating film attributable to the gate electrode can be suppressed,enabling a more reliable transistor to be formed.

Where the oxide film thickness is 1.8 nm, the threshold (Vth) range ofMOSFET predictable from the effective work function is as shown in FIG.4 relative to the channel impurity concentration. According to thepresent invention which uses a crystallized Ni silicide electrode whoseeffective work function can be modulated to 4.0 eV or less for nMOS or5.2 eV or more for pMOS by adding impurity elements, a high performancedevice having a low threshold of around 0.1 V, a level that cannot beachieved by using a conventional impurity element-doped NiSi electrodein the channel concentration of usual CMOS devices (10¹⁷ to 10¹⁸ cm⁻³)can be realized.

According to the invention, it is preferable for the crystallized Nisilicide constituting the gate electrode to be less than 40 atom % in Nicontent. An Ni content of less than 40 atom % enables the gate electrodeto adhere more tightly to the gate insulating film such as silicon oxidefilm (SiO₂ film) and silicon oxynitride film (SiON film), and almostcompletely prevents electrode-attributable stress from occurring, makingit possible to enhance the reliability of MOSFETs.

According to the invention, it is preferable for the Ni content of thecrystallized Ni silicide constituting the gate electrode to be not lessthan 5 atom %, more preferable to be not less than 10 atom %, from theviewpoints of restraining gate depletion and reducing gate resistance;it is further preferable to be not less than 20 atom %, more preferableto be not less than 25 atom % and especially preferable to be not lessthan 30 atom % from the viewpoint of threshold control. Taking intoconsideration the threshold control aspect in addition to theaforementioned reliability enhancement, it is preferable for this Nicontent to be not more than 38 atom %, more preferable to be not morethan 35%. Incidentally, the Ni content is represented in a percentage ofratio of the Ni quantity to the total quantity of Ni and Si (Ni/(Ni+Si))in terms of the number of atoms. Thus, Ni silicides represented byNi_(x)Si_(1-x) (0.1≦x<0.4) is preferable with a view to restraining gatedepletion, reducing gate resistance and improving the reliability, andconsidering threshold control in addition to these points,Ni_(x)Si_(1-x) (0.2≦x<0.4) is more preferable. It is further preferablefor x in these formulas to be in the preferable range for the Ni contentfrom the viewpoints stated above.

It is preferable for the gate electrode according to the invention, witha view to achieving a desired effective work function, to have theregion of the crystallized silicide having the Ni content as statedabove extending for 5 nm or more, more preferable to have it for 10 nmor more, in the thickness direction (the direction perpendicular to thesubstrate plane) from the gate electrode/insulating film interface.

As the doped crystallized Ni silicide electrode as stated above isapplied to the gate electrode according to the invention, when a CMOSdevice is to be fabricated, Ni silicide electrodes for nMOS and pMOS canbe formed at a single silicidation step as will be described afterwards.Accordingly, the number of steps can be reduced and the processsimplified, resulting in a cost saving.

As the gate insulating film in the invention, a silicon oxide film (SiO₂film) or a silicon oxynitride film (SiON film) can be used. Also, a highdielectric constant insulating film, such as an HfSiON film may be usedas the gate insulating film. In this case, though the range of thresholdvariation due to impurity addition is smaller than where SiO₂ and SiONgate insulating films are used, the variation of the effective workfunction can be increased by placing a silicon oxide film, a siliconoxynitride film or a silicon nitride film in the part in contact withthe gate electrode, and this would enable a low threshold to be realizedin MOSFETs. Between the high dielectric constant insulating film and thesilicon substrate, a silicon oxide film or a silicon oxynitride film mayas well be provided.

FIG. 1 shows a schematic sectional view of a CMOSFET structure in whicha doped Ni silicide is used as the gate electrode. In the figure,reference numeral 1 designates a silicon substrate; 2, an elementseparation region; 3, a gate insulating film; 6, an extension diffusionregion; 7, a gate side wall; 8, a source-drain diffusion region; 11, aninterlayer insulating film; 13, an n-type full silicide gate electrode;14, a p-type full silicide gate electrode; and 19 and 20, segregatedimpurities regions. Such a CMOS structure can achieve, in addition tothe effect of avoiding gate electrode depletion, high performancetransistors considered impractical so far with a high level ofreliability and reproducibility.

If fluorine atoms are provided in the silicon substrate of the pMOSregion at least in the part in contact with the gate insulating film inaddition to the configuration described above, the effective workfunction of the gate electrode can be increased by about 0.1 eV, therebyenabling the threshold in pMOS to be reduced by about 0.1 V. Also, ifnitrogen atoms are provided in the silicon substrate of the nMOS regionat least in the part in contact with the gate insulating film, theeffective work function of the gate electrode can be reduced by about0.1 eV, thereby enabling the threshold in nMOS to be lowered by about0.1 V.

According to the invention, the work function of the gate electrode ofpMOS and the work function of the gate electrode of nMOS, as statedabove, can be controlled with the composition of the silicide making upthe gate electrode and impurities contained in the silicide. Thus, thecrystallized silicides of the same composition can be formed as the gatematerials in the pMOS region and the nMOS region, with the silicide ofthe pMOS region and the silicide of the nMOS region containing differentimpurities. Therefore, in the manufacturing process according to theinvention, after the formation of the gate material over the gateinsulating film, no step to remove this gate material needs to becarried out, and gate electrodes having different work functions betweenpMOS and nMOS can be formed. For this reason, the surface of the gateinsulating film is not exposed to the wet etching liquid or an organicsolvent, and accordingly the quality of the gate insulating film is notadversely affected. As a result, highly reliable CMOS devices can befabricated. Furthermore, as the addition of impurities to the gatematerial can be accomplished accurately by an already establishedtechnique, such as ion implantation, fluctuations of the threshold canbe restrained.

The invention will be described more specifically below with referenceto drawings.

FIRST EXEMPLARY EMBODIMENT

FIGS. 5( a) through 5(h), FIGS. 6( i) through 6(j) are sectional viewsshowing a MOSFET manufacturing process pertaining to a first exemplaryembodiment of the invention.

First, the element separation region 2 was formed in the surface regionof the silicon substrate 1 by applying the STI (Shallow TrenchIsolation) technique. Then, the gate insulating film 3 made up of SiONwas formed over the element-separated silicon substrate surface.

Next, as shown in FIG. 5( a), a poly-Si film 4 of 80 nm in thickness wasformed over the gate insulating film 3 and, by carrying out ionimplantation in combination with a usual PR process using a resist,different impurity elements were ion-implanted into the nMOS region andthe pMOS region of this poly-Si film. As was implanted into the nMOSregion, and B, into the pMOS region. The implantation energy and doseswere respectively 5 KeV and 5×10¹⁵ cm⁻² for As and 2 KeV and 6×10¹⁵ cm⁻²for B.

After that, a silicon oxide film 5 of 150 nm in thickness was stacked asshown in FIG. 5( b).

Next, as shown in FIG. 5( c), the stacked poly-Si film 4 and siliconoxide film 5 were processed using the lithography technique and the RIE(Reactive Ion Etching) technique to form a gate electrode pattern. Then,ion implantation was carried out using the gate electrode pattern asmask to form the extension diffusion region 6 in a self-matching mannerThis step was performed for each of the nMOS region and the pMOS region.

Next, the gate side wall 7 was formed as shown in FIG. 5( d) bydepositing a silicon nitride film and a silicon oxide film in successionand etching them back after that.

Next, one of the nMOS region and the pMOS region was masked and ionimplantation was again carried out into the other region to form thesource-drain diffusion region 8. This step was performed on each of thenMOS region and the pMOS region. The source-drain diffusion region isactivated by subsequent heat treatment.

Next, as shown in FIG. 5( e), a metal film 9 of 20 nm in thickness wasdeposited all over by sputtering, and a silicide layer 10 of about 40 nmin thickness was formed solely in the source-drain diffusion region bythe salicide technique using the gate electrode pattern, the gate sidewall and the element separation region as masks (FIG. 5( f)). As thissilicide layer 10, an Ni monosilicide (NiSi) layer that could minimizethe contact resistance was formed. Instead of such an Ni silicide, a Cosilicide or a Ti silicide may as well be used.

Next, as shown in FIG. 5( g), the interlayer insulating film 11 made upof a silicon oxide film was formed by the CVD (Chemical VaporDeposition) method.

This interlayer insulating film 11 was flattened by the CMP (ChemicalMechanical Polishing) technique, followed by etching back the interlayerinsulating film as shown in FIG. 5( h) to expose the poly-Si film 4 ofthe gate electrode pattern.

Next, as shown in FIG. 6( i), an Ni film 12 for siliciding the poly-Sifilm 4 of the gate electrode pattern part was deposited. The Ni filmthickness at this step is so set that NiSi₂ is formed in the part incontact with the gate insulating film when poly-Si and Ni havesufficiently reacted to form the silicide. In this exemplary embodiment,an Ni film of 25 nm was formed by DC magnetron sputtering at roomtemperature.

After that, gate electrodes 13 and 14 made up of crystallized NiSi₂ wereformed by causing poly-Si and Ni to sufficiently react with each otherby heat treatment at 650° C. for two minutes. In this silicidation, thedopant (As) in the silicide electrode of the nMOS region segregated inthe vicinities of the electrode/insulating film interface as shown inFIG. 60) to form a laminar segregated impurities region 19. The dopant(B) in the silicide electrode of the pMOS region also segregated in thevicinities of the electrode/insulating film interface as shown in FIG.60) to form a laminar segregated impurities region 20.

Finally, the superfluous Ni film which was not silicided at the heattreatment step was removed by wet etching using an aqueous solution ofsulfuric acid-hydrogen peroxide. After that, a contact plug and upperlayer wiring (not shown) were formed by usual methods.

By going through these steps, the CMOS structure having full silicideelectrodes in which impurity elements differing between the nMOS regionand the pMOS region are segregated in the vicinities of theelectrode/insulating film interface as shown in FIG. 60) was formed. Inthe MOSFET fabricated in this way, the effective work function of thesilicide electrode was 4.0 eV for nMOS and 5.2 eV for pMOS.

FIG. 7( a) shows the dependence of the drain current on the gate voltagein nMOS having a gate electrode (NiSi₂ electrode) whose effective workfunction has been modulated to 4.0 eV. The channel concentration is5×10¹⁷ cm⁻³, and the Vth predictable from the effective work function of4.0 eV shown in FIG. 4 is 0.1 V. According to FIG. 7( a), the Vth ofnMOS having the NiSi₂ electrode is 0.1 V as predicted from the effectivework function. It was further confirmed that the electron mobility inthis transistor could have a comparable value to that of a transistorusing poly-Si for the gate electrode and SiO₂ for the gate insulatingfilm.

FIG. 7( b) shows the gate voltage dependence of the drain current ofpMOS having a gate electrode (NiSi₂ electrode) whose effective workfunction has been modulated to 5.2 eV. The channel concentration is5×10¹⁷ cm⁻³, and the Vth predictable from the effective work function of5.2 eV shown in FIG. 4 is −0.1 V. According to FIG. 7( b), the Vth ofpMOS having an NiSi₂ electrode is −0.1 V as predicted from the effectivework function. It was further confirmed that the electron mobility inthis transistor could have a comparable value to that of a transistorusing poly-Si for the gate electrode and SiO₂ for the gate insulatingfilm.

Incidentally, even when other p-type dopant impurities (Al, In, Ga, TI)than B were added to the Ni full silicide electrode for pMOS and othern-type dopant impurities (N, P, Sb, Bi) than As were added to the Nifull silicide electrode for nMOS, similar effects were achieved.

Further, where a crystallized NiSi₂ electrode is used as the gateelectrode, as it tightly adheres to the gate insulating film made up ofSiO₂ or SiON (silicon oxynitride film) and stress attributable to thegate electrode hardly occurs, highly reliable MOSFETs can be provided,

When a CMOS device is to be fabricated, according to the invention, Nifull silicide electrodes for nMOS and pMOS can be formed at a singlesilicidation step and accordingly the process can be simplified,resulting in a saving in manufacturing cost.

As hitherto revealed, excellent transistor performance characteristicscan be achieved by combining a crystallized Ni full silicide electrode(NiSi₂ electrode) to which impurity elements have been added and an SiONgate insulating film.

COMPARATIVE EXAMPLE

A silicided layer was formed according to the method disclosed inJapanese Patent Application Laid-Open No. 2005-129551 (Patent Document2) as follows: a poly-Si film was formed via a thermal oxide film over asilicon substrate; an Ni film was formed over it; and heat treatment wasconducted at 400° C. for one minute to cause a siliciding reaction totake place. In accordance with this process, silicided layers differingin Ni content were formed by forming Ni films differing in thicknessover poly-Si films having the certain thickness, and subjecting them tothe heat treatment. The impurity concentration in the silicided layersin the vicinities of its interface with the insulating film was 10²¹cm⁻³ or more.

Measurement of the XRD spectrum of the silicided layers that were formedrevealed, especially where ratio of the nickel film thickness(T_(Ni))/poly-Si film thickness (T_(Si)) was smaller than 0.55, no peakaccompanying crystallization, or the intensity of the peak was extremelyweak; namely the silicided layers that were formed were found eithernon-crystalline or very low in crystallinity.

FIG. 8 shows the relationship between the Ni content of the silicidedlayer (silicide electrode) of the MOS capacitance (the composition inthe vicinities of the interface between the silicided layer and theinsulating film) and the Ni/poly-Si film thickness ratio (T_(Ni)/T_(Si))before silicidation. This Ni content was figured out from XPSmeasurement. The error bars of the Ni content in the diagram representfluctuations in the multi-point XPS measurement. It is seen from thisdiagram that the Ni content in the silicided layer continuously varieswith the T_(Ni)/T_(Si) ratio.

FIG. 9 shows the effective work functions of the silicided layer in theundoped case along with the cases of As addition and B addition. It isseen from this diagram that, in the undoped case, the effective workfunction of the silicided layer rises with an increase in the Nicontent. Therefore, fluctuations of the Ni content by about ±5%, forinstance, would cause threshold fluctuations by 0.1 to 0.2 V or so. Thistendency is entirely different from the case of the crystallized Ni fullsilicide electrode formed in accordance with the embodiment of theinvention as described above. This difference in effective work functionvariation attributable to the electrode composition is probably due tothe difference in crystallinity ensuing from the difference in formationmethod. While silicidation is achieved by heat treatment at 400° C. forone minute according to the method disclosed in Patent Document 2, thesilicided layer that was obtained was found either non-crystalline orvery low in crystallinity as stated above. On the other hand, as thesiliciding conditions according to the embodiment of the invention are400° C. for five minutes where T_(Ni)/T_(Si) is 0.55 or above and 650°C. for two minutes where T_(Ni)/T_(Si) is less than 0.55, an Ni silicideelectrode of superior crystallinity is formed, and an Ni silicideelectrode of high crystallinity is formed especially when T_(Ni)/T_(Si)is less than 0.55.

FIG. 9 also shows the effective work functions of silicided layersformed by the method described in Patent Document 2, doped withimpurities (As and B). It is seen from this diagram that, in the dopedcases as well, the effective work function rises with an increase in theNi content of the parent silicided layer. Thus, no significant increasein the variation of the effective work function according to the Nicontent (the difference between the case in which any impurity has beenadded and the undoped case) is observed. This tendency is entirelydifferent from the case of the crystallized Ni full silicide electrodeformed in accordance with the invention. Thus in the crystallized Nifull silicide electrode according to the invention, the variation of theeffective work function increases with a decrease in the Ni content (anincrease in the Si content). This difference in theelectrode-composition dependence of effective work function variationattributable to the addition of impurities is probably due to thedifference in crystallinity ensuing from the difference in formationmethod as in the undoped case described above.

Further, the effective work function of the doped silicided layer formedby the method described in Patent Document 2 was found to be about 4.1eV where the Ni content was 30 to 60 atom % and n-type impurities werecontained, while the effective work function of about 5.1 eV wasobtained where the Ni content was 40 to 70 atom % and p-type impuritieswere contained, but no Ni silicide electrode having an effective workfunction that could realize a threshold required for the highperformance nMOS and pMOS (4.0 eV for nMOS, 5.2 eV for pMOS) wasobtained. Further, as the adhesion between Ni and SiO₂ gate insulatingfilms is very weak especially where the Ni content is 40 atom % or more,coming-off frequently occurred on the silicided layer/insulating filminterface. Moreover, when the Ni content is 40 atom % or more, acompressive stress on the gate insulating film attributable to thesilicided layer works on the insulating film, causing a drop in thereliability of the gate insulating film.

Further, as the doped silicided layer formed by the method described inPatent Document 2 is not an Ni silicide of a stoichiometric compositionas is stated in Patent Document 2 itself, the heat treatment after theformation causes the content distribution in the layer to vary,resulting in an observation that the effective work functionsignificantly fluctuated. FIG. 10 shows the fluctuation of thethresholds of transistors using doped crystallized NiSi formed accordingto the invention, as the gate electrodes, and also shows the fluctuationof the thresholds of transistors using doped Ni silicided layer (the Nicontent was 33.3%, the same as NiSi₂) formed by the method described inPatent Document 2, as the gate electrodes. In the case according to theembodiment of the invention, the absolute quantity of the fluctuationwas 4 mV. In the case according to Patent Document 2, the absolutequantity of the fluctuation was 150 mV.

SECOND EXEMPLARY EMBODIMENT

FIGS. 11( a) through 11(h), FIGS. 12( i) through 12(k) and FIGS. 13( l)through 13(n) are sectional views showing a MOSFET manufacturing processaccording to a second exemplary embodiment of the invention.

In this exemplary embodiment, the following steps are included: forminga silicide layer in the source-drain diffusion region after thesilicidation for gate electrode formation; and forming a silicon nitridefilm to distort the channel of the MOSFET, thereby enhancing electronmobility.

As the steps until the source-drain diffusion region formation (FIGS.11( a) through 11(d)) are similar to their counterparts in the firstexemplary embodiment (FIGS. 6( a) through 6(d)), their description willbe dispensed with, and the description will refer to the next step (FIG.11( e)) onward. Incidentally in this exemplary embodiment, Sb was addedto the poly-Si film in the nMOS region, and In, to the poly-Si film inthe pMOS region.

A silicon nitride film 15 was formed all over by the CVD method as shownin FIG. 11( e). This nitride film has the role of protecting thesubstrate and the like when the interlayer insulating film 11 is removedby wet processing afterwards.

Next, the interlayer insulating film 11 made up of a silicon oxide filmwas formed by the CVD method as shown in FIG. 11( f).

This interlayer insulating film 11 was flattened by the CMP technique,and then the poly-Si film 4 of the gate electrode pattern was exposed byetching back the interlayer insulating film as shown in FIG. 11( g).

Next, as shown in FIG. 11( h), the Ni film 12 for siliciding the poly-Sifilm 4 of the gate electrode pattern was deposited. The Ni filmthickness at this step is to be so set that, when poly-Si and Nisufficiently react with each other to form a silicide, the compositionof part in contact with the gate insulating film become NiSi₂. In thisexemplary embodiment, an Ni film of 25 nm was formed by DC magnetronsputtering at room temperature.

After that, crystallized NiSi₂ electrodes 13 and 14 were formed bycausing poly-Si and Ni to sufficiently react with each other by heattreatment at 650° C. for two minutes. In this silicidation, the dopant(Sb) in the silicide electrode of the nMOS region segregated in thevicinities of the electrode/insulating film interface as shown in FIG.12( i) to form a laminar segregated impurities region 19. The dopant(In) in the silicide electrode of the pMOS region also segregated in thevicinities of the electrode/insulating film interface as shown in FIG.12( i) to form a laminar segregated impurities region 20.

After that, the superfluous Ni film which was not silicided at the heattreatment step was removed by wet etching.

Next, as shown in FIG. 12( j), the interlayer insulating film 11 wasremoved with an aqueous solution of hydrofluoric acid, followed by theremoval of the silicon nitride film 15 with phosphoric acid.

Next, a metal film of 20 nm in thickness was deposited all over bysputtering, and the silicide layer 10 of about 40 nm in thickness wasformed solely in the source-drain diffusion region by the salicidetechnique using the gate electrode, the gate side wall and the elementseparation region as masks (FIG. 12( k)). As this silicide layer 10, anNi monosilicide (NiSi) layer that could minimize the contact resistancewas formed. Instead of such an Ni silicide, a Co silicide or a Tisilicide may as well be used.

Next, as shown in FIG. 13( l), a silicon nitride film 16 was formed allover by the CVD method, in order to apply a tensile stress to the n-typechannel, thereby enhancing electron mobility.

Next, as shown in FIG. 13( m), the silicon nitride film 16 over the pMOSregion was subjected to ion implantation by carrying out ionimplantation in combination with a usual PR process using a resist, andthe stress on the silicon nitride film 16 was thereby eased.

Next, as shown in FIG. 13( n), an interlayer insulating film 17 ofsilicon oxide film was formed by the CVD method.

Finally, a contact plug and upper layer wiring (not shown) by usualmethods were formed, and thus a CMOS structure having full silicide gateelectrodes 13 and 14 in which impurity elements differing between thenMOS region and the pMOS region are segregated in the vicinities of theelectrode/insulating film interface was obtained. In the MOSFETfabricated in this way, the effective work function of the full silicideelectrode 13 was 4.0 eV for nMOS and 5.2 eV for pMOS.

In this exemplary embodiment too, as in the first exemplary embodiment,Vth is 0.1 V for nMOS and −0.1 V for pMOS as predicted from theeffective work function. It was further confirmed that the electronmobility in this transistor could have a comparable value to that of atransistor using poly-Si for the gate electrode and SiO₂ for the gateinsulating film.

Incidentally, even when other p-type impurities (B, Al, Ga, TI) than Inwere added to the Ni full silicide electrode for pMOS and other n-typeimpurities (N, P, As, Bi) than Sb were added to the Ni full silicideelectrode for nMOS, similar effects were achieved.

As hitherto described, excellent transistor performance characteristicscan be achieved by combining a crystallized Ni full silicide electrode(NiSi₂ electrode) to which impurity elements have been added and an SiONgate insulating film.

THIRD EXEMPLARY EMBODIMENT

FIGS. 15( a) through 15(e) are sectional views showing a MOSFETmanufacturing process according to a third exemplary embodiment of theinvention. This exemplary embodiment includes, with a view to realizinga lower threshold, a step of ion-implanting fluorine into the siliconsubstrate of the pMOS region where the p-channel is to be formed andnitrogen into the silicon substrate of the nMOS region where then-channel is to be formed.

First, as shown in FIG. 15( a), the element separation region 2 wasformed in the surface region of the silicon substrate 1 by applying theSTI (Shallow Trench Isolation) technique.

Then, as shown in FIG. 15( b), an nMOS region 101 and a pMOS region 102were formed in the element-separated silicon substrate surface by usingthe usual lithography step and ion implantation. The impurityconcentration in the substrate forming the channel was set to betweenabout 5×10¹⁷ and 1018 cm⁻³ to restrain device deterioration due to theshort-channel effect in the minute MOSFET.

Next, as shown in FIG. 15( c), sacrificial oxide films 103 and 104 ofrespectively about 16 nm and 3 nm in thickness were formed over thesurfaces of the nMOS region 101 and the pMOS region 102.

After that, by using a usual lithography step and ion implantation in astate in which one of the regions is masked, fluorine was ion-implantedinto the nMOS region 101 and nitrogen, into the pMOS region 102 of thesilicon substrate from over the sacrificial oxide films 103 and 104. Theimplantation energy and doses were, for instance, 15 KeV and 1×10¹⁵cm⁻², respectively for both fluorine and nitrogen. The quantities ofnitrogen 105 and fluorine 106 immediately underneath the sacrificialoxide films 103 and 104 were assayed by the SIMS method, and found to beboth about 1×10²⁰ cm⁻³.

Next, heat treatment was performed at 900° C. for about 10 seconds,followed by removal of the sacrificial oxide films 103 and 104 with asolution of hydrofluoric acid.

Then, as shown in FIG. 15( d), an SiO₂ gate insulating film 3 of 1.8 nmin thickness was formed.

After the formation of the gate insulating film 3, a similar process tothe MOSFET manufacturing process pertaining to the first exemplaryembodiment was carried to form a CMOS shown in FIG. 16. This CMOS hasNiSi₂ full silicide gate electrodes 13 and 14 that have, in thevicinities of the gate electrode/insulating film interface, segregatedimpurity regions in which the dopant elements differing between pMOS andnMOS (an n-type impurity 19 such as As for the nMOS region and a p-typeimpurity 20 such as B for the pMOS region) are segregated, and the CMOSfurther has the fluorine 105 in the p-channel region and the nitrogen106 in the n-channel region. The quantities of the nitrogen 105 and thefluorine 106 in the silicon substrate immediately underneath the SiO₂gate insulating film 3 in the fabricated MOSFET were assayed by the SIMSmethod, and found to be about 1×10¹⁹ cm⁻³ and 1×10¹⁷ cm⁻³, respectively.

FIG. 17 shows the threshold of pMOS in the MOSFET fabricated asdescribed above when the quantity of fluorine in the silicon substrateafter the MOSFET formation is varied by varying the implantationquantity of fluorine. The absolute value of the threshold drops with anincrease in the quantity of fluorine, reaching about 0.1 V at a fluorinequantity of about 1×10¹⁷ cm⁻³. As is seen from FIG. 17, from theviewpoint of substantially varying the threshold, it is preferable forthe quantity of fluorine in the channel immediately underneath the gateinsulating film to be 1×10¹⁶ cm⁻³ or more, more preferable to be 5×10¹⁵cm⁻³ or more. On the other hand, if the quantity of fluorine surpasses2×10¹⁷ cm⁻³, the junction leak in the source-drain region tends toincrease on account of crystalline defect formation accompanying ionimplantation. Further, if the quantity of fluorine surpasses 5×10¹⁷cm⁻³, accelerated oxidation is promoted, resulting in a tendency to makedifficult the control of the gate insulating film of 2 nm or less inthickness required for the formation of a minute CMOS device. Therefore,from the viewpoint of restraining accelerated oxidation and crystallinedefect formation accompanying ion implantation, it is preferable for thequantity of fluorine in the channel immediately underneath the gateinsulating film to be 5×10¹⁷ cm⁻³ or less, more preferable to be 2×10¹⁷cm⁻³ or less.

FIG. 18 shows the threshold of nMOS in the MOSFET fabricated asdescribed above when the quantity of nitrogen in the silicon substrateafter the MOSFET formation is varied by varying the implantationquantity of nitrogen. The threshold drops with an increase in thequantity of nitrogen, reaching about 0.1 V at a nitrogen quantity ofabout 1×10¹⁹ cm⁻³. As is seen from FIG. 18, from the viewpoint ofsubstantially varying the threshold, it is preferable for the quantityof nitrogen in the channel immediately underneath the gate insulatingfilm to be 1×10¹⁸ or more, more preferable to be 5×10¹⁸ cm⁻³ or more. Onthe other hand, if the quantity of nitrogen is too great, especially ifit surpasses 1×10²⁰ cm⁻³, the reliability of the gate insulating filmtends to deteriorate. Therefore, from the viewpoint of restraining thedeterioration of the reliability of the gate insulating film, it ispreferable for the quantity of nitrogen in the channel immediatelyunderneath the gate insulating film to be 1×10²⁰ cm⁻³ or less, morepreferable to be 5×10¹⁹ cm⁻³ or less.

As indicated with reference to this exemplary embodiment, by combining agate electrode made up of a crystallized Ni full silicide substantiallyhaving an NiSi₂ composition to which impurities have been added and asilicon substrate having a region containing fluorine or nitrogen in thevicinities of the gate insulating film/silicon substrate interface, aCMOS device whose threshold is much lower than that of the firstexemplary embodiment can be obtained.

Although exemplary embodiments of the present invention have beendescribed so far, the invention is not limited to these exemplaryembodiments, but can be implemented by appropriately selecting materialsand structure without deviating from the spirit thereof.

For instance, if it is desired to reduce the gate leak current, aso-called high dielectric constant insulating film such as HfSiON can beused as the gate insulating film. In this case, the threshold variationwould be less than in cases where a silicon oxide film or a siliconoxynitride film is used. However, as shown in FIG. 14, by placing asilicon oxide film, silicon a oxynitride film or a silicon nitride filmas a cap film 22 intervening between the gate electrode and the highdielectric constant insulating film 21, the effective work function canbe reduced with the result of realizing a low threshold. Between thehigh dielectric constant insulating film and the substrate, a siliconoxide film or a silicon oxynitride film may as well be provided.

Incidentally in this specification, the “effective work function” of thegate electrode is usually figured out from a flat band by CVmeasurement, and is influenced by a fixed charge in the insulating film,a dipole formed on the interface, a Fermi level pinning and so forthbesides the gate electrode's own work function. It is distinguished fromthe essential “work function” of the material making up the gateelectrode. Further, the term “high dielectric constant insulating film”is used to distinguish it from the insulating film made up of silicondioxide (SiO₂) conventionally used as the gate insulating film, andmeans that it has a higher dielectric constant than that of silicondioxide, but its specific value is not limited by this term.

1. A semiconductor device comprising: a silicon substrate; and a fieldeffect transistor comprising a gate insulating film over the siliconsubstrate, a gate electrode on the gate insulating film, and source anddrain regions, wherein said gate electrode comprises, at least in partin contact with said gate insulating film, a crystallized Ni silicideregion containing an impurity element of a conductivity type opposite toa conductivity type of a channel region in the field effect transistor.2. The semiconductor device according to claim 1, wherein the silicidemaking up said crystallized Ni silicide region is of a compositionrepresented by Ni_(x)Si_(1-x)(0.2≦x<0.4).
 3. The semiconductor deviceaccording to claim 1, wherein the silicide making up said crystallizedNi silicide region comprises an NiSi₂ phase.
 4. The semiconductor deviceaccording to claim 1, wherein said silicon substrate comprises, at leastin part in contact with the gate insulating film, a region containingfluorine atoms in the case of a P-channel transistor and a regioncontaining nitrogen atoms in the case of an N-channel transistor.
 5. Asemiconductor device comprising: a silicon substrate; a P-channel fieldeffect transistor comprising a first gate insulating film over saidsilicon substrate, a first gate electrode on the first gate insulatingfilm, and first source and drain regions; and an N-channel field effecttransistor comprising g a second gate insulating film over said siliconsubstrate, a second gate electrode on the second gate insulating film,and second source and drain regions, wherein the first gate electrodecomprises, at least in part in contact with the first gate insulatingfilm, a crystallized Ni silicide region containing p-type impurities,and the second gate electrode comprises, at least in part in contactwith the second gate insulating film, a crystallized Ni silicide regioncontaining n-type impurities.
 6. The semiconductor device according toclaim 5, wherein the silicides making up the crystallized Ni silicideregions of the first and second gate electrodes are of a compositionrepresented by Ni_(x)Si_(1-x)(0.2≦x<0.4).
 7. The semiconductor deviceaccording to claim 5, wherein the silicides making up the crystallizedNi silicide regions of the first and second gate electrodes comprisesNiSi₂ phases.
 8. The semiconductor device according to claim 5, whereinthe first and second gate electrodes comprise, in respective parts incontact with the first and second gate insulating films, regionscontaining an impurity element of a higher concentration than above theregions.
 9. The semiconductor device according to claim 5, wherein thefirst and second gate electrodes comprise, in respective parts incontact with the first and second gate insulating films, regions havingimpurity concentration of 1×10²⁰ cm⁻³ or above.
 10. The semiconductordevice according to claim 5, wherein the first and second gateinsulating films are silicon oxide films or silicon oxynitride films.11. The semiconductor device according to claim 5, wherein the first andsecond gate insulating films comprise silicon oxide films, siliconoxynitride films or silicon nitride films respectively in contact withthe first and second gate electrodes.
 12. The semiconductor deviceaccording to claim 5, wherein said silicon substrate comprises, at leastin part in contact with the first gate insulating film, a regioncontaining fluorine atoms.
 13. The semiconductor device according toclaim 5, wherein said silicon substrate comprises, at least in part incontact with the second gate insulating film, a region containingnitrogen atoms.
 14. A method of manufacturing the semiconductor deviceas recited in claim 5, comprising: providing a silicon substratecomprising an n-type active region and a p-type active region; forming ainsulating film for first and second gate insulating films over saidsilicon substrate; forming a silicon film for gate over said insulatingfilm; adding p-type impurities to said silicon film for gate in a regionwhere a P-channel field effect transistor is to be formed; adding n-typeimpurities to said silicon film for gate in a region where an N-channelfield effect transistor is to be formed; forming a gate pattern byprocessing said silicon film for gate; forming first source and drainregions in the region where the P-channel field effect transistor is tobe formed; forming second source and drain regions in the region wherethe N-channel field effect transistor is to be formed; forming aninterlayer insulating film so as to cover said gate pattern; removingupper part of the interlayer insulating film so as to expose said gatepattern; forming a nickel film over the exposed gate pattern; conductingheat treatment to silicide said gate pattern, thereby forming first andsecond gate electrodes; and selectively removing superfluous nickel ofunsilicided part of said nickel film.
 15. The semiconductor devicemanufacturing method according to claim 14, wherein the p-typeimpurities and the n-type impurities are added by ion implantation. 16.The semiconductor device according to claim 14, further comprising:adding fluorine to the silicon substrate in the region where theP-channel field effect transistor is to be formed before forming theinsulating film for the first and second gate insulating films.
 17. Thesemiconductor device according to claim 14, further comprising: addingnitrogen to the silicon substrate in the region where the N-channelfield effect transistor is to be formed before forming the insulatingfilm for the first and second gate insulating films.